Timer Prescaler Input Form
Enter your source clock, timing target, counter mode, and timer width. The calculator searches for practical PSC and ARR combinations automatically.
Formula Used
1) Timer input clock
Timer Clock = Source Clock ÷ Input Divider
2) Timer tick frequency
Tick Frequency = Timer Clock ÷ (PSC + 1)
3) Edge aligned update period
Period = (ARR + 1) ÷ Tick Frequency
4) Center aligned update period
Period = 2 × (ARR + 1) ÷ Tick Frequency
5) Frequency from period
Frequency = 1 ÷ Period
6) Relative error
Error % = |Achieved Period - Target Period| ÷ Target Period × 100
How to Use This Calculator
- Enter the timer source clock in hertz.
- Select the divider that feeds the timer input clock.
- Choose whether your design target is a period or frequency.
- Enter the target value and matching unit.
- Select the timer width and the counter mode.
- Set the largest allowed PSC register value.
- Optionally raise the minimum ARR value to improve resolution.
- Press the calculate button to view the best PSC and ARR combinations.
- Review the graph, compare timing error, then export the results as CSV or PDF.
Example Data Table
| Source Clock | Divider | Target | Timer Width | Mode | PSC | ARR | Achieved Result | Error |
|---|---|---|---|---|---|---|---|---|
| 48 MHz | ÷1 | 1 ms | 16-bit | Edge aligned | 47 | 999 | 1.000000 ms | 0.000000000 % |
| 72 MHz | ÷1 | 20 kHz | 16-bit | Edge aligned | 71 | 49 | 20.000000 kHz | 0.000000000 % |
| 84 MHz | ÷2 | 10 ms | 16-bit | Center aligned | 83 | 2499 | 10.000000 ms | 0.000000000 % |
Frequently Asked Questions
1) What does a timer prescaler do?
It divides the incoming timer clock before the counter advances. A larger prescaler slows the tick rate, extends the possible period range, and reduces timing granularity.
2) Why are PSC and ARR both needed?
PSC sets the tick speed. ARR sets how many ticks occur before overflow or update. Together they define the final timer period and update frequency.
3) When should I use center aligned mode?
Use it when symmetric timing matters, especially for PWM generation. It doubles the count travel, so the same PSC and ARR produce a longer cycle than edge aligned counting.
4) Why is my requested timing not exact?
Exact timing requires an integer PSC and ARR pair. Many targets fall between valid register values, so the calculator ranks the nearest practical combinations by error.
5) Does timer width matter?
Yes. Wider timers support larger ARR values. That expands the reachable period range and often improves resolution because more count values become available.
6) Why would I raise the minimum ARR value?
A larger minimum ARR often improves duty-cycle resolution and makes waveform tuning smoother. Very small ARR values still work, but adjustment steps become coarse.
7) Can this calculator help with PWM base frequency?
Yes. Use your desired PWM base frequency as the target. Then apply compare values separately in firmware to create the required duty cycle.
8) How do I verify the chosen setting on hardware?
Load PSC and ARR, run the timer, then measure the interrupt period or output waveform with an oscilloscope or logic analyzer. Compare it against the achieved result shown here.